1. Field of the Invention
The present invention generally relates to increasing speed and reducing the height of a logic circuit stack, such as an NMOS (n-channel metal-oxide-semiconductor) logic circuit stack or a PMOS (p-channel metal-oxide-semiconductor) logic circuit stack, by removing a conventional footer circuit from the stack and using one of the parameters from the stack to enable the relocated footer.
2. Description of the Related Art
Dynamic CMOS (complementary metal-oxide-semiconductor) logic achieves higher performance than straight CMOS logic by precharging the output node of the gates and subsequently discharging it when the logic function to be computed requires it. Through this scheme, only n-type FETs (field effect transistors) are needed to compute the logical function. Since n-type FETs are inherently faster than p-type FETs, there is a speed advantage. However, this speed advantage comes with a cost since extra transistors must be added to the logic function to properly time the precharge and computation operations.
FIG. 1 shows a dynamic logic gate that uses inputs A, B, and C to compute the logic function A*(B+C). FET 101 is used to precharge the output node to a low voltage. FET 102 is used to prevent the evaluation of the output node during precharge and is called a “footer device”.
FIG. 2 shows a similar circuit with separate compute and precharge signals. It is advantageous to separate these two signals in multi-phase domino logic and asynchronous logic design styles.
Dynamic logic is very efficient as long as one can implement complex boolean functions in each gate. The complexity of the gate is determined by the highest stack of n-type FETs in the pulldown network (FETs 108, 109, 110, and 111 in FIG. 2) that can safely be used. For current CMOS technology, that height is about three or four FETs, one of which is the computation FET (i.e., the footer). The delay through the gate also increases very rapidly with the height of the pull-down stack. This is a problem.